Conventional digital signal processing applications commonly increase or decrease a sample rate of an input signal. Functionally, to decrease the sample rate, a data sequence is applied to an anti-aliasing Low Pass Filter (LPF) and a sample rate reduction module.
In a conventional sample rate reduction process, the ratio of an output clock frequency to an input clock frequency is fixed or limited to a set of fractions. As the frequency of the input clock changes, the ratio between the frequency of the input clock and the frequency of the output clock also changes, degrading the signal quality in a typical fixed or multi-rate down-sampling process. Adaptive data rate conversion (ADRC) is a conventional design that allows the input clock rate (or frequency) to change relative to the output clock rate (or frequency), while maintaining signal quality at the output of the conversion process. Such a conventional design adapts to a change in the input sample clock and computes samples at the fixed output clock rate.
The purpose of adaptive data rate conversion is to accurately interpolate a signal at a new output clock rate as the period of the input clock changes in relationship to the period of the output clock. Adaptive data rate conversion adapts to a change in the input sample clock by tracking the relationship between the period of the input clock and the period of the output clock. By accurately estimating the output sample period as the input sample period changes, adaptive data rate conversion accurately interpolates the resampled signal at the output clock rate.
The simplest way to translate a digital signal from one clock domain to another is to pass the digitized signal through a digital-to-analog converter (D/A) and then resample the data through an analog-to-digital converter (A/D) at the output clock rate. However, such an approach is costly in terms of both silicon area and power. Such an approach simply changes the sample points on a band-limited waveform, which is the concept behind a simple data rate converter.
To pass a digital signal between two different clock domains, the data rate is changed (or converted) from the old data rate to the new data rate. Such a conversion is typically done by finding a common ratio between the nominal input data rate and the nominal output rate. A filter can be designed that will either (i) interpolate the incoming data if the input data rate is lower than the output data rate, or (ii) decimate the incoming data if the incoming data rate is higher than the output data rate. In either technique, the filter weights N samples of the incoming data to provide a single unique sample of the output data, while maintaining or providing the planned bandwidth.
A digital approach is preferred since it can be implemented in a smaller silicon area and at considerably lower power. However, unlike the analog approach (which is to a large extent ignorant of the input and output frequencies so long as they meet Nyquist limits) the data converter provides only the correct output waveform when the input data rate and output data rate are at predetermined nominal values. Therefore, if the input data rate changes, the frequency of the normalized output waveform is changed with respect to the output data rate.
Data rate conversion is typically based on the ratio of the input data rate and the output data rate. In the case of sampled data system, the frequency of the input data can vary with the sample clock that introduces errors into the conversion process.
Referring to FIG. 1, a block diagram of a circuit 10 is shown illustrating a fixed down sampling process. The circuit 10 includes a low pass filter (LPF) circuit 12 and a sample clock reduction circuit 14. The LPF 102 may be an anti-aliasing low pass filter. In a typical down-sampling process, an input data sequence is applied to the low pass filter 12 and the circuit 14. The circuit 12 has an input 20 that receives an input data sequence signal (IN), an input 22 that receives an input sample clock signal FS and an output 24 that presents a signal INT. The circuit 12 has an input 26 that receives the signal INT, an input 28 that receives an output sample clock signal and an output 30 that presents an output data sequence (e.g., OUT).
Referring to FIG. 2, a diagram is shown illustrating a time response with fixed down sampling. A continuous time waveform 50 is sampled periodically at a number of input sample points 52a-52d by the input and output sample clock. The input sample points 52a-52d are interpolated to calculate output sample points 54a-54b sampled at a longer period. A typical fixed rate down sampling process computes the output samples shown in FIG. 2. The input sampling clock period is represented by arrow 56. The output sampling clock period is represented by arrow 58.
Referring to FIG. 3, a diagram is shown illustrating an example of time response amplitude error with fixed down sampling. In any resampling system, the resampled signal is estimated at a multiple of the estimated output sample period. In a fixed down sampling system, the output sample period is estimated as a fixed ratio of the input sample period. Further, the fixed down sampling process does not track a change in the relationship between the input clock period and the output clock period. If the input sample period decreases, the estimated output clock period also decreases. Similarly, if the input clock period increases, the estimated output clock period also increases. Therefore, in a fixed down-sampling process, the estimated period of the output clock varies in proportion to the input clock period. As the period of the input clock changes, the time at which the resampled signal amplitude is estimated also changes, causing an amplitude error in the estimated resampled signal.
FIG. 3 shows an example of a reduction in the input sample period 56′ with no change in the output sample clock period 58. Due to the fixed sample-rate reduction ratio, the estimated output samples 54a and 54b are computed at incorrect times 60a and 60b. As shown, the actual output sampling instants 62a and 62b are computed as a function of the input sample period 56′. Since the input sample period 56′ has been reduced as compared with FIG. 1, the estimated output sample period has also been reduced, causing errors 64a and 64b in the estimated amplitude of the signal 50 at the output clock rate. Instead of computing the amplitude of the signal 50 at the output sample points 54a and 54b, the sample points 62a and 62b are calculated at time 60a and 60b, respectively.
It would be desirable to overcome problems associated with conventional data rate converters by measuring the change in the input data rate and adjust the filter coefficients to provide a stable data rate conversion process whatever the input data rate.